Without testing, it is not possible to determine whether all the circuits on an integrated circuit operate according to the design. Conventional semiconductor devices are tested by sequentially providing a series of so-called test vectors to exercise each component contained in the integrated circuit. As the complexity of the integrated circuit increases, the number of test vectors necessarily also increases. This can result in a test taking an unreasonably long time in the sense that it becomes uneconomical to test the device.
It is widely known that present day semiconductor devices can have two modes of operation. They either operate in a test mode or a functional mode. The test mode allows the semiconductor device to be checked structurally without requiring the semiconductor device to receive all the test vectors associated with the semiconductor device while operating in the normal, functional mode. Structural testing generally is a quicker and more efficient method of checking and detecting process defects compared to receiving all the required inputs to check the functionality of the device in the functional mode.
During normal use, the semiconductor device generally remains in the functional mode. Typically, the semiconductor device operates in this test mode only twice during its lifetime; the test mode may be utilized during the manufacturing and quality control processes such as the wafer sorting procedure and the final testing procedure.
By operating the semiconductor device in the test mode of operation, defects within the semiconductor device which are discoverable during full operation are quickly and efficiently found. Prior semiconductor devices required a dedicated test mode pin on the semiconductor package to properly configure the semiconductor device into either the test mode or the functional mode.
For example, FIG. 1 illustrates a sample prior art implementation of a dedicated test mode pin on a semiconductor package to prevent shared global signals from disturbing the functional mode. A test mode pin 10 and an input/output pin 20 are an integral part of a semiconductor device 5. The test mode pin 10 is dedicated to receiving a signal either placing the semiconductor device 5 either into the test mode or the functional mode. The test mode pin 10 is also coupled to a first input of an AND gate 30. Further, the input/output pin 20 is coupled to a second input of the AND gate 30. In this particular example, when the test mode pin 10 receives a high signal, the semiconductor device 5 operates in the test mode. While in the test mode, the first input of the AND gate 30 also remains high such that the output of the AND gate 30 will mirror the input from the input/output pin 20 as represented by a lead line 40. On the other hand, when the test mode pin 10 is low, the semiconductor device 5 operates in the functional mode. Additionally, when the test mode pin 10 is low, the output from the AND gate 30 is held low regardless of the input from the input/output pin 20.
This sample prior art implementation as shown in FIG. 1 relies on combinational logic to control whether the semiconductor device 5 operates in the test mode or the functional mode. In essence, the signal on the test mode pin 10 either passes or blocks the signal on the input/output pin 20 at the output of the AND gate 30. As a result, the current state of the test mode pin 10 determines the present operating mode of the semiconductor device 5. Accordingly in this example, for the semiconductor device 5 to remain operating in the test mode, the test mode pin 10 must remain high. Similarly, if the test mode pin 10 is pulled low, then the semiconductor device 5 immediately operates in the functional mode. Because any change in state of the test mode pin 10 also changes the mode of operation of the semiconductor device 5, the test mode pin 10 cannot be shared with any other function besides determining the mode of operation of the semiconductor device 5.
Unfortunately, many types of semiconductor devices 5 are pin limited, in that the circuit either does not have sufficient space to provide an additional bond pad or the package does not have sufficient pins to allow for a special purpose test pin. To add the extra area to the semiconductor device 5 or an extra pin to the package can be prohibitively expensive. There is a higher cost associated with having the test mode pin 10 dedicated to the mode of operation of the semiconductor device 5. Adding an additional pin to the semiconductor device 5 may not be possible without using a bigger pin count package. This separate, dedicated connection increases the manufacturing costs for each semiconductor device produced.
What is needed is an apparatus and method for utilizing a single pin of a semiconductor device to determine the operating mode of the semiconductor device and also to serve as an input/output interface for the semiconductor.